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ds093 (v3.2) march 8, 2007 www.xilinx.com 1 product specification ? 2002-2007 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as lis ted at http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. features ? optimized for 1.8v systems - as fast as 5.7 ns pin-to-pin delays - as low as 13 a quiescent current ? industry?s best 0.18 micron cmos cpld - optimized architecture for effective logic synthesis - multi-voltage i/o operation ? 1.5v to 3.3v ? available in multiple package options - 100-pin vqfp with 80 user i/o - 144-pin tqfp with 100 user i/o - 132-ball cp (0.5mm) bga with 100 user i/o - pb-free available for all packages ? advanced system features - fastest in system programming 1.8v isp using ieee 1532 (jtag) interface - ieee1149.1 jtag boundary scan test - optional schmitt-trigger input (per pin) - unsurpassed low power management datagate enable (dge) signal control - two separate i/o banks - realdigital 100% cmos product term generation - flexible clocking modes optional dualedge triggered registers clock divider (divide by 2,4,6,8,10,12,14,16) coolclock - global signal options with macrocell control multiple global clocks with phase selection per macrocell multiple global output enables global set/reset - advanced design security - open-drain output option for wired-or and led drive - pla architecture superior pinout retention 100% product term routability across function block - optional bus-hold, 3-state or weak pull-up on selected i/o pins - optional configurable grounds on unused i/os - mixed i/o voltages compatible with 1.5v, 1.8v, 2.5v, and 3.3v logic levels sstl2-1, sstl3-1, and hstl-1 i/o compatibility - hot pluggable refer to the coolrunner?-ii family data sheet for architec- ture description. description the coolrunner-ii 128-macrocell device is designed for both high performance and low power applications. this lends power savings to high-end communication equipment and high speed to battery operated devices. due to the low power stand-by and dynamic operation, overall system reli- ability is improved this device consists of eight function blocks inter-con- nected by a low power advanced interconnect matrix (aim). the aim feeds 40 true and complement inputs to each function block. the function blocks consist of a 40 by 56 p-term pla and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. additionally, these registers can be globally reset or preset and configured as a d or t flip-flop or as a d latch. there are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. a schmitt-trigger input is available on a per input pin basis. in addition to stor- ing macrocell output states, the macrocell registers may be configured as direct input registers to store signals directly from input pins. clocking is available on a global or function block basis. three global clocks are available for all function blocks as a synchronous clock source. macrocell registers can be individually configured to power up to the zero or one state. a global set/reset control line is also available to asynchro- nously set or reset selected registers during operation. additional local clock, synchronous clock-enable, asynchro- nous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-function block basis. a dualedge flip-flop feature is also available on a per mac- rocell basis. this feature allows high performance synchro- nous operation based on lower frequency clocking to help reduce the total power consumption of the device. circuitry has also been included to divide one externally supplied global clock (gck2) by eight different selections. this yields divide by even and odd clock frequencies. the use of the clock divide (division by 2) and dualedge flip-flop gives the resultant coolclock feature. datagate is a method to selectively disable inputs of the cpld that are not of interest during certain points in time. 0 xc2c128 coolrunner-ii cpld ds093 (v3.2) march 8, 2007 00 product specification r
xc2c128 coolrunner-ii cpld 2 www.xilinx.com ds093 (v3.2) march 8, 2007 product specification r by mapping a signal to the datagate function, lower power can be achieved due to reduction in signal switching. another feature that eases voltage translation is i/o bank- ing. two i/o banks are available on the coolrunner-ii 128 macrocell device that permit easy interfacing to 3.3v, 2.5v, 1.8v, and 1.5v devices. the coolrunner-ii 128 macrocell cpld is i/o compatible with various jedec i/o standards (see table 1 ). this device is also 1.5v i/o compatible with the use of schmitt-trigger inputs. realdigital design technology xilinx coolrunner-ii cplds are fabricated on a 0.18 micron process technology which is derived from leading edge fpga product development. coolrunner-ii cplds employ realdigital technology, a design technique that makes use of cmos technology in both the fabrication and design methodology. realdigital technology employs a cascade of cmos gates to implement sum of products instead of tradi- tional sense amplifier methodology. due to this technology, xilinx coolrunner-ii cplds achieve both high-perfor- mance and low power operation. supported i/o standards the coolrunner-ii 128 macrocell features lvcmos, lvttl, sstl and hstl i/o implementations. see ta b le 1 for i/o standard voltages. the lvttl i/o standard is a gen- eral purpose eia/jedec standard for 3.3v applications that use an lvttl input buffer and push-pull output buffer. the lvcmos standard is used in 3.3v, 2.5v, 1.8v applications. both hstl and sstl make use of a v ref pin for jedec compliance. coolrunner-ii cplds are also 1.5v i/o com- patible with the use of schmitt-trigger inputs. table 1: i/o standards for xc2c128 (1) iostandard attribute output v ccio input v ccio input v ref board termination voltage v tt lvttl 3.3 3.3 n/a n/a lvcmos33 3.3 3.3 n/a n/a lvcmos25 2.5 2.5 n/a n/a lvcmos18 1.8 1.8 n/a n/a lvcmos15 (2) 1.5 1.5 n/a n/a hstl_1 1.5 1.5 0.75 0.75 sstl2_1 2.5 2.5 1.25 1.25 sstl3_1 3.3 3.3 1.5 1.5 (1) for information on assigning vref pins, see xapp399 (2) lvcmos15 requires use of schmitt-trigger inputs. figure 1: i cc vs frequency table 2: i cc vs frequency (lvcmos 1.8v t a = 25c) (1) frequency (mhz) 0 25 50 75 100 150 175 200 225 250 typical i cc (ma) 0.019 3.97 7.95 11.92 15.89 23.83 27.80 31.93 35.73 39.70 notes: 1. 16-bit up/down, resetable binary counter (one counter per function block). frequency (mhz) ds093_041905 i cc (ma) 0 250 200 150 100 50 20 40 0
xc2c128 coolrunner-ii cpld ds093 (v3.2) march 8, 2007 www.xilinx.com 3 product specification r recommended operating conditions dc electrical characteristics (over recommended operating conditions) absolute maximum ratings symbol description value units v cc supply voltage relative to ground ?0.5 to 2.0 v v ccio supply voltage for output drivers ?0.5 to 4.0 v v jtag (2) jtag input voltage limits ?0.5 to 4.0 v v ccaux jtag input supply voltage ?0.5 to 4.0 v v in (1) input voltage relative to ground ?0.5 to 4.0 v v ts (1) voltage applied to 3-state output ?0.5 to 4.0 v t stg (3) storage temperature (ambient) ?65 to +150 c t j junction temperature + 150 c notes: 1. maximum dc undershoot below gnd must be limited to either 0.5v or 10 ma, whichever is easiest to achieve. during transitions, the device pins may undershoot to ?2.0v or overshoot to +4.5v, provided this over or undershoot lasts less than 10 ns and with t he forcing current being limited to 200 ma. 2. valid over commercial temperature range. 3. for soldering guidelines and thermal considerations, see the device packaging information on the xilinx website. for pb-free packages, see xapp427 . symbol parameter min max units v cc supply voltage for internal logic and input buffers commercial t a = 0c to +70c 1.7 1.9 v industrial t a = ?40c to +85c 1.7 1.9 v v ccio supply voltage for output drivers @ 3.3v operation 3.0 3.6 v supply voltage for output drivers @ 2.5v operation 2.3 2.7 v supply voltage for output drivers @ 1.8v operation 1.7 1.9 v supply voltage for output drivers @ 1.5v operation 1.4 1.6 v v ccaux supply voltage for jtag programming 1.7 3.6 v symbol parameter test conditions typical max. units i ccsb standby current commercial v cc = 1.9v, v ccio = 3.6v 30 120 a i ccsb standby current industrial v cc = 1.9v, v ccio = 3.6v 60 200 a i cc (1) dynamic current f = 1 mhz - 500 a f = 50 mhz - 10 ma c jtag jtag input capacitance f = 1 mhz - 10 pf c clk global clock input capacitance f = 1 mhz - 12 pf c io i/o capacitance f = 1 mhz - 10 pf i il (2) input leakage current v in = 0v or v ccio to 3.9v - +/?1 a i ih (2) i/o high-z leakage v in = 0v or v ccio to 3.9v - +/?1 a notes: 1. 16-bit up/down, resetable binary counter (one counter per function block). 2. see quality and reliability section in coolrunner-ii family data sheet for details.
xc2c128 coolrunner-ii cpld 4 www.xilinx.com ds093 (v3.2) march 8, 2007 product specification r lvcmos and lvttl 3.3v dc voltage specifications lvcmos 2.5v dc voltage specifications (1) the v ih max value represents the jedec specification for lvcmos25. the coolrunner-ii input buffer can tolerate up to 3.9v without physical damage. lvcmos 1.8v dc voltage specifications (1) the v ih max value represents the jedec specification for lvcmos18. the coolrunner-ii input buffer can tolerate up to 3.9v without physical damage. lvcmos 1.5v dc voltage specifications (1) symbol parameter test conditions min. max. units v ccio input source voltage 3.0 3.6 v v ih high level input voltage 2.0 3.9 v v il low level input voltage ?0.3 0.8 v v oh high level output voltage i oh = ?8 ma, v ccio = 3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 3v v ccio ? 0.2v - v v ol low level output voltage i ol = 8 ma, v ccio = 3v - 0.4 v i ol = 0.1 ma, v ccio = 3v - 0.2 v symbol parameter test conditions min. max. units v ccio input source voltage 2.3 2.7 v v ih high level input voltage 1.7 v ccio + 0.3 (1) v v il low level input voltage ?0.3 0.7 v v oh high level output voltage i oh = ?8 ma, v ccio = 2.3v v ccio ?0.4v - v i oh = ?0.1 ma, v ccio = 2.3v v ccio ? 0.2v - v v ol low level output voltage i ol = 8 ma, v ccio = 2.3v - 0.4 v i ol = 0.1 ma, v ccio = 2.3v - 0.2 v symbol parameter test conditions min. max. units v ccio input source voltage 1.7 1.9 v v ih high level input voltage 0.65 x v ccio v ccio + 0.3 (1) v v il low level input voltage ?0.3 0.35 x v ccio v v oh high level output voltage i oh = ?8 ma, v ccio = 1.7v v ccio ? 0.45 - v i oh = ?0.1 ma, v ccio = 1.7v v ccio ? 0.2 - v v ol low level output voltage i ol = 8 ma, v ccio = 1.7v - 0.45 v i ol = 0.1 ma, v ccio = 1.7v - 0.2 v symbol parameter test conditions min. max. units v ccio input source voltage 1.4 1.6 v v t+ input hysteresis threshold voltage 0.5 x v ccio 0.8 x v ccio v v t- 0.2 x v ccio 0.5 x v ccio v v oh high level output voltage i oh = ?8 ma, v ccio = 1.4v v ccio ? 0.45 v i oh = ?0.1 ma, v ccio = 1.4v v ccio ? 0.2 v
xc2c128 coolrunner-ii cpld ds093 (v3.2) march 8, 2007 www.xilinx.com 5 product specification r schmitt trigger input dc voltage specifications sstl2-1 dc voltage specifications sstl3-1 dc voltage specifications hstl1 dc voltage specifications v ol low level output voltage i ol = 8 ma, v ccio = 1.4v 0.4 v i ol = 0.1 ma, v ccio = 1.4v 0.2 v notes: 1. hysteresis used on 1.5v inputs. symbol parameter test conditions min. max. units v ccio input source voltage 1.4 3.9 v v t+ input hysteresis threshold voltage 0.5 x v ccio 0.8 x v ccio v v t- 0.2 x v ccio 0.5 x v ccio v symbol parameter test conditions min. typ. max. units v ccio input source voltage 2.3 2.5 2.7 v v ref (1) input reference voltage 1.15 1.25 1.35 v v tt (2) termination voltage v ref ? 0.04 1.25 v ref + 0.04 v v ih high level input voltage v ref + 0.18 - 3.9 v v il low level input voltage ?0.3 - v ref ? 0.18 v v oh high level output voltage i oh = ?8 ma, v ccio = 2.3v v ccio ? 0.62 - - v v ol low level output voltage i ol = 8 ma, v ccio = 2.3v - - 0.54 v notes: 1. v ref should track the variations in v ccio , also peak to peak ac noise on v ref may not exceed 2% v ref. 2. v tt of transmitting device must track v ref of receiving devices. symbol parameter test conditions min. typ. max. units v ccio input source voltage 3.0 3.3 3.6 v v ref (1) input reference voltage 1.3 1.5 1.7 v v tt (2) termination voltage v ref ? 0.05 1.5 v ref + 0.05 v v ih high level input voltage v ref + 0.2 - v ccio + 0.3 v v il low level input voltage ?0.3 - v ref ? 0.2 v v oh high level output voltage i oh = ?8 ma, v ccio = 3v v ccio ? 1.1 - - v v ol low level output voltage i ol = 8 ma, v ccio = 3v - - 0.7 v notes: 1. v ref should track the variations in v ccio , also peak to peak ac noise on v ref may not exceed 2% v ref. 2. v tt of transmitting device must track v ref of receiving devices. symbol parameter test conditions min. typ. max. units v ccio input source voltage 1.4 1.5 1.6 v v ref (1) input reference voltage 0.68 0.75 0.90 v v tt (2) termination voltage v ccio x 0.5 v v ih high level input voltage v ref + 0.1 - 1.9 v v il low level input voltage ?0.3 - v ref ? 0.1 v symbol parameter test conditions min. max. units
xc2c128 coolrunner-ii cpld 6 www.xilinx.com ds093 (v3.2) march 8, 2007 product specification r v oh high level output voltage i oh = ?8 ma, v ccio = 1.7v v ccio -0.4 - - v v ol low level output voltage i ol = 8 ma, v ccio = 1.7v - - 0.4 v notes: 1. v ref should track the variations in v ccio , also peak to peak ac noise on v ref may not exceed 2% v ref. 2. v tt of transmitting device must track v ref of receiving devices. symbol parameter test conditions min. typ. max. units
xc2c128 coolrunner-ii cpld ds093 (v3.2) march 8, 2007 www.xilinx.com 7 product specification r ac electrical characteristics over recommended operating conditions symbol parameter -6 -7 units min. max. min. max. t pd1 propagation delay single p-term - 5.7 - 7.0 ns t pd2 propagation delay or array - 6.0 - 7.5 ns t sud direct input register set-up time 3.6 - 4.6 - ns t su1 setup time fast (single p-term) 2.4 - 3.0 - ns t su2 setup time (or array) 2.7 - 3.5 - ns t hd direct input register hold time 0.0 - 0.0 - ns t h hold time (or array or p-term) 0.0 - 0.0 - ns t co clock to output - 4.2 - 5.4 ns f toggle (1) internal toggle rate - 450 - 300 mhz f system1 (2) maximum system frequency - 244 - 152 mhz f system2 (2) maximum system frequency - 227 - 141 mhz f ext1 (3) maximum external frequency - 152 - 119 mhz f ext2 (3) maximum external frequency - 145 - 112 mhz t psud direct input register p-term clock setup time 2.5 - 3.1 - ns t psu1 p-term clock setup time (single p-term) 1.3 - 1.5 - ns t psu2 p-term clock setup time (or array) 1.6 - 2.0 - ns t phd direct input register p-term clock hold time 0.2 - 0.2 - ns t ph p-term clock hold 0.7 - 1.0 - ns t pco p-term clock to output - 5.9 - 7.3 ns t oe /t od global oe to output enable/disable - 5.9 - 7.5 ns t poe /t pod p-term oe to output enable/disable - 7.0 - 8.5 ns t moe /t mod macrocell driven oe to output enable/disable - 7.7 - 9.9 ns t pao p-term set/reset to output valid - 6.6 - 8.1 ns t ao global set/reset to output valid - 5.0 - 7.6 ns t suec register clock enable setup time 3.1 - 3.5 - ns t hec register clock enable hold time 0.0 - 0.0 - ns t cw global clock pulse width high or low 1.1 - 1.6 - ns t aprpw asynchronous preset/reset pulse width (high or low) 6.0 - 7.5 - ns t pcw p-term pulse width high or low 6.0 - 7.5 - ns t dgsu set-up before datagate latch assertion 0.0 - 0.0 - ns t dgh hold to datagate latch assertion 4.0 - 6.0 - ns t dgr datagate recovery to new data - 8.2 - 9.0 ns t dgw datagate low pulse width 3.0 - 4.0 - ns t cdrsu cdrst setup time before falling edge gclk2 1.3 - 2.0 - ns t cdrh hold time cdrst after falling edge gclk2 0.0 - 0.0 - ns t config (4) configuration time - 350 - 350 us notes: 1. f toggle is the maximum clock frequency to which a t flip-flop can reliably toggle (see the coolrunner-ii family data sheet). 2. f system1 is the internal operating frequency for a device with 16-bit resetable binary counter through one p-term per macrocell while f system2 is through the or array (one counter per function block). 3. f ext1 (1/t su1 +t co ) is the maximum external frequency using one p-term while f ext2 is through the or array. 4. typical configuration current during t config is 10 ma.
xc2c128 coolrunner-ii cpld 8 www.xilinx.com ds093 (v3.2) march 8, 2007 product specification r internal timing parameters symbol parameter (1) -6 -7 units min. max. min. max. buffer delays t in input buffer delay - 2.0 - 2.6 ns t din direct data register input delay - 3.7 - 5.3 ns t gck global clock buffer delay - 1.5 - 2.1 ns t gsr global set/reset buffer delay - 1.6 - 3.5 ns t gts global 3-state buffer delay - 2.1 - 3.0 ns t out output buffer delay - 2.3 - 2.6 ns t en output buffer enable/disable delay - 3.8 - 4.5 ns p-term delays t ct control term delay - 1.2 - 1.4 ns t logi1 single p-term delay adder - 0.5 - 1.1 ns t logi2 multiple p-term delay adder - 0.3 - 0.5 ns macrocell delay t pdi input to output valid - 0.9 - 0.7 ns t ldi setup before clock (transparent latch) - 2.1 - 2.5 ns t sui setup before clock 1.4 - 1.4 - ns t hi hold after clock 0.0 - 0.0 - ns t ecsu enable clock setup time 1.4 - 1.6 - ns t echo enable clock hold time 0.0 - 0.0 - ns t coi clock to output valid - 0.4 - 0.7 ns t aoi set/reset to output valid - 1.1 - 1.5 ns t cdbl clock doubler delay - 0.0 - 0.0 ns feedback delays t f feedback delay - 1.8 - 3.4 ns t oem macrocell to global oe delay - 2.0 - 2.6 ns i/o standard time adder delays 1.5v cmos t hys15 hysteresis input adder - 3.0 - 4.0 ns t out15 output adder - 0.8 - 1.0 ns t slew15 output slew rate adder - 4.0 - 4.0 ns i/o standard time adder delays 1.8v cmos t hys18 hysteresis input adder - 2.0 - 4.0 ns t in18 input adder - 0 - 0 ns t out18 output adder - 0.0 - 0.0 ns t slew18 output slew rate adder - 2.5 - 4.0 ns
xc2c128 coolrunner-ii cpld ds093 (v3.2) march 8, 2007 www.xilinx.com 9 product specification r switching characteristics figure 2: derating curve for t pd switching test conditions figure 3: ac load circuits i/o standard time adder delays 2.5v cmos t in25 standard input adder - 0.6 - 0.7 ns t hys25 hysteresis input adder - 1.5 - 3.0 ns t out25 output adder - 0.8 - 0.9 ns t slew25 output slew rate adder - 3.0 - 4.0 ns i/o standard time adder delays 3.3v cmos/ttl t in33 standard input adder - 0.5 - 0.6 ns t hys33 hysteresis input adder - 1.2 - 3.0 ns t out33 output adder - 1.2 - 1.4 ns t slew33 output slew rate adder - 3.0 - 4.0 ns i/o standard time adder delays hstl, sstl sstl2-1 input adder to t in , t din , t gck , t gsr , t gts - 0.8 - 2.5 ns output adder to t out - 0.5 - 0.5 ns sstl3-1 input adder to t in , t din , t gck , t gsr , t gts - 0.8 - 2.5 ns output adder to t out - 0.5 - 0.5 ns hstl-1 input adder to t in , t din , t gck , t gsr , t gts - 2.0 - 2.5 ns output adder to t out - 0.0 - 0.0 ns notes: 1. 1.5 ns input pin signal rise/fall. internal timing parameters (continued) symbol parameter (1) -6 -7 units min. max. min. max. number of outputs switching 12 4 8 16 4.0 4.4 4.8 v cc = v ccio = 1.8v, 25 o c t pd2 (ns) 5.0 4.6 4.2 ds093_02_050103 r 1 v cc c l r 2 device under test output type lvttl33 lvcmos33 lvcmos25 lvcmos18 lvcmos15 r 1 268 275 188 112.5 150 r 2 235 275 188 112.5 150 c l 35 pf 35 pf 35 pf 35 pf 35 pf ds092_03_092302 test point notes: 1. c l includes test fixtures and probe capacitance. 2. 1.5 nsec maximum rise/fall times on inputs.
xc2c128 coolrunner-ii cpld 10 www.xilinx.com ds093 (v3.2) march 8, 2007 product specification r typical i/v output curves the i/v curve illustrates the nominal amount of current that an i/o can source/sink at different voltage levels. 11 figure 4: typical i/v curves for xc2c128 vo (output volts) xc128_iv_all_050703 io (output current ma) 0 0 40 10 50 20 30 60 3.0 2.5 2.0 1.5 1.0 .5 3 .5 3.3v 1.5v 1.8v 2.5v iol pin descriptions function block macro- cell vq100 cp132 tq144 i/o bank 1 1 13 g1 17 2 12-f1162 1 3 12 f2 15 2 1411f3142 1 5 10 e1 13 2 169e2122 17---- 18---- 19---- 110---- 1118e3112 1127d1102 1136d292 114-c172 1(gts1) 15 4 c2 6 2 1(gts0) 16 3 c3 5 2 21-g2191 2 2 14 g3 21 1 2 3 15 h1 22 1 2 4 16 h2 23 1 2 5 17 h3 24 1 2 6 18 j1 25 1 27---- 28---- 29---- 210---- 21119j2261 212-k1281 2(gck0) 13 22 k3 30 1 2(gck1) 14 23 l2 32 1 2(cdrst) 15 24 m2 35 1 2(gck2) 16 27 n2 38 1 pin descriptions (continued) function block macro- cell vq100 cp132 tq144 i/o bank
xc2c128 coolrunner-ii cpld ds093 (v3.2) march 8, 2007 www.xilinx.com 11 product specification r 31-b142 3(gts3) 2 2 b2 3 2 3(gts2) 3 1 a1 2 2 3(gsr) 4 99 a3 143 2 3597b41402 3696a41382 3795c51362 38---- 39---- 310---- 31194b51342 312 a51332 31393c61322 31492b61312 31591a61302 31690c71292 4(dge) 1 28 p2 39 1 42-m3401 43-n3411 4 4 29 p3 43 1 4 5 30 m4 45 1 4 6 32 m5 49 1 4 7 33 n5 50 1 48---- 49---- 410---- 41134p5511 41235m6521 41336n6531 41437p6541 41539n7561 41640m7571 pin descriptions (continued) function block macro- cell vq100 cp132 tq144 i/o bank 5165g13942 5266g12952 5367f14962 54-f13972 5568f12982 56-e131002 5 7 70 e12 101 2 58---- 59---- 510---- 51171d141022 51272d131032 51373d121042 51474c141052 51576b131102 5 16 - a13 111 2 6164h12921 6263h13911 6361j13881 6460j12871 6559k14861 6658k13851 67---- 68---- 69---- 610---- 6 11 - l14 83 1 6 12 56 l13 82 1 6 13 - l12 81 1 6 14 55 m14 80 1 615-m13791 6 16 54 m12 78 1 pin descriptions (continued) function block macro- cell vq100 cp132 tq144 i/o bank
xc2c128 coolrunner-ii cpld 12 www.xilinx.com ds093 (v3.2) march 8, 2007 product specification r 7 1 77 c12 112 2 7 2 78 b12 113 2 73-a121152 7 4 79 c11 116 2 7 5 80 b11 117 2 7 6 81 a11 118 2 77-c101192 78---- 79---- 710---- 71182a101202 712-c91212 71385a81242 71486b81252 71587c81262 71689b71282 pin descriptions (continued) function block macro- cell vq100 cp132 tq144 i/o bank 8 1 - n14 77 1 8253n13761 8352p14741 8450p12711 85-m11701 8649n11691 87---- 88---- 89---- 810---- 811-p11681 8 12 46 p10 64 1 81344p9611 81443m8601 81542n8591 81641p8581 notes: 1. gts = global output enable, gsr = global reset/set, gck = global clock, cdrst = clock divide reset, dge = datagate enable. 2. gck, gsr, and gts pins can also be used for general purpose i/o. pin descriptions (continued) function block macro- cell vq100 cp132 tq144 i/o bank
xc2c128 coolrunner-ii cpld ds093 (v3.2) march 8, 2007 www.xilinx.com 13 product specification r xc2c128 jtag, power/ground, no connect pins and total user i/o ordering information pin type vq100 (1) cp132 (1) tq144 (1) tck 48 m10 67 tdi 45 m9 63 tdo 83 b9 122 tms 47 n10 65 v ccaux (jtag supply voltage) 5 d3 8 power internal (v cc ) 26, 57 p1, k12, a2 1, 37, 84 power bank 1 i/o (v ccio1 ) 20, 38, 51 j3, p7, g14, p13 27, 55, 73, 93 power bank 2 i/o (v ccio2 ) 88, 98 a14, c4, a7 109, 127, 141 ground 21, 25, 31, 62, 69, 75, 84, 100 k2, n1, p4, n9, n12, j14, h14, e14, b14, a9, b3 29, 36, 47, 62, 72, 89, 90, 99, 108, 123, 144 no connects - l1, l3, m1, n4, c13, b10 18, 20, 31, 33, 34, 42, 44, 46, 48, 66, 75, 106, 107, 114, 135, 137, 139, 142 total user i/o (including dual function pins) 80 100 100 notes: 1. pin compatible with all larger and smaller densities except where i/o banking is used. part number pin/ball spacing ja (c/watt) jc (c/watt) package type package body dimensions i/o comm. (c) ind. (i) (1) xc2c128-6vq100c 0.5mm 47.5 12.5 very thin quad flat pack 14mm x 14mm 80 c xc2c128-7vq100c 0.5mm 47.5 12.5 very thin quad flat pack 14mm x 14mm 80 c XC2C128-6CP132C 0.5mm 72.4 15.7 chip scale package 8mm x 8mm 100 c xc2c128-7cp132c 0.5mm 72.4 15.7 chip scale package 8mm x 8mm 100 c xc2c128-6tq144c 0.5mm 46.1 7.9 thin quad flat pack 20mm x 20mm 100 c xc2c128-7tq144c 0.5mm 46.1 7.9 thin quad flat pack 20mm x 20mm 100 c xc2c128-6vqg100c 0.5mm 47.5 12.5 very thin quad flat pack; pb-free 14mm x 14mm 80 c xc2c128-7vqg100c 0.5mm 47.5 12.5 very thin quad flat pack; pb-free 14mm x 14mm 80 c xc2c128-6cpg132c 0.5mm 72.4 15.7 chip scale package; pb-free 8mm x 8mm 100 c xc2c128-7cpg132c 0.5mm 72.4 15.7 chip scale package; pb-free 8mm x 8mm 100 c xc2c128-6tqg144c 0.5mm 46.1 7.9 thin quad flat pack; pb-free 20mm x 20mm 100 c xc2c128-7tqg144c 0.5mm 46.1 7.9 thin quad flat pack; pb-free 20mm x 20mm 100 c xc2c128-7vq100i 0.5mm 47.5 12.5 very thin quad flat pack 14mm x 14mm 80 i
xc2c128 coolrunner-ii cpld 14 www.xilinx.com ds093 (v3.2) march 8, 2007 product specification r device part marking note: due to the small size of chip scale packages, the complete ordering part number cannot be included on the package marking. part marking on chip scale packages by line are: ? line 1 = x (xilinx logo) then truncated part number ? line 2 = not related to device part number ? line 3 = not related to device part number ? line 4 = package code, speed, operating temperature, three digits not related to device part number. package codes: c5 = cp132, c6 = cpg132. xc2c128-7cp132i 0.5mm 72.4 15.7 chip scale package 8mm x 8mm 100 i xc2c128-7tq144i 0.5mm 46.1 7.9 thin quad flat pack 20mm x 20mm 100 i xc2c128-7vqg100i 0.5mm 47.5 12.5 very thin quad flat pack; pb-free 14mm x 14mm 80 i xc2c128-7cpg132i 0.5mm 72.4 15.7 chip scale package; pb-free 8mm x 8mm 100 i xc2c128-7tqg144i 0.5mm 46.1 7.9 thin quad flat pack; pb-free 20mm x 20mm 100 i notes: c = commercial (t a = 0 c to +70 c); i = industrial (t a = ?40 c to +85 c) . figure 5: sample package with part marking part number pin/ball spacing ja (c/watt) jc (c/watt) package type package body dimensions i/o comm. (c) ind. (i) (1) standard example: xc2c128 device speed grade package type number of pins temperature range -6 tq c 144 pb- free example: xc2c128 tq g 144 c device speed grade package type pb -free number of pins -6 temperature range xc2cxxx tq144 7c device type package speed operating range this line not related to device part number part marking for all non chip scale packages r
xc2c128 coolrunner-ii cpld ds093 (v3.2) march 8, 2007 www.xilinx.com 15 product specification r figure 6: vq100 very thin quad flat pack vq100 top view gnd i/o (3) vccio2 i/o i/o i/o i/o i/o i/o i/o i/o i/o v ccio2 i/o i/o i/o gnd tdo i/o i/o i/o i/o i/o i/o i/o vcc i/o (2) i/o (5) i/o i/o gnd i/o i/o i/o i/o i/o i/o vccio1 i/o i/o i/o i/o i/o i/o tdi i/o tms tck i/o i/o gnd i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o vcc i/o i/o i/o i/o i/o vccio1 i/o (1) i/o (1) i/o (1) i/o (1) v aux i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vccio1 gnd i/o (2) i/o (2) i/o (4) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 (1) - global output enable (2) - global clock (3) - global set/reset (4) - clock divide reset (5) - data gate
xc2c128 coolrunner-ii cpld 16 www.xilinx.com ds093 (v3.2) march 8, 2007 product specification r figure 7: cp132 chip scale package cp132 bottom view p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vcc vccio1 vccio1 gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o(5) i/o i/o vaux i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vccio1 i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o gnd i/o i/o i/o vccio1 i/o gnd i/o i/o i/o i/o(2) vcc i/o gnd nc i/o nc i/o i/o i/o(2) i/o(1) vccio2 i/o i/o i/o(3) i/o i/o i/o gnd i/o i/o i/o vccio2 vcc i/o i/o i/o i/o gnd i/o i/o i/o tdo nc i/o i/o gnd i/o(1) i/o i/o nc vccio2 i/o(1) i/o i/o i/o i/o i/o i/o i/o i/o i/o(1) nc i/o i/o i/o i/o i/o i/o i/o tdi tck i/o i/o i/o i/o(4) gnd i/o i/o nc i/o i/o i/o i/o gnd tms i/o gnd i/o i/o(2) (1) - global output enable (2) - global clock (3) - global set/reset (4) - clock divide reset (5) - datagate enable
xc2c128 coolrunner-ii cpld ds093 (v3.2) march 8, 2007 www.xilinx.com 17 product specification r warranty disclaimer these products are subject to the terms of the xilinx limited warranty which can be viewed at http://www.xilinx.com/warranty.htm . this limited warranty does not extend to any use of the products in an application or environment that is not within the specifications stated on the then-current xilinx data sheet for the produc ts. products are not designed to be fail-safe and are not warranted for use in applications th at pose a risk of physical harm or loss of life. use of products in such applications is fully at the risk of customer subject to applicable laws and regulations. figure 8: tq144 thin quad flat pack v cc i/o (1) i/o (1) i/o i/o (1) i/o (1) i/o v aux i/o i/o i/o i/o i/o i/o i/o i/o i/o nc i/o nc i/o i/o i/o i/o i/o i/o v ccio1 i/o gnd i/o (2) nc i/o (2) nc nc i/o (4) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 tq144 top view v cc i/o (2) i/o (5) i/o i/o nc i/o nc i/o nc gnd nc i/o i/o i/o i/o i/o i/o v ccio1 i/o i/o i/o i/o i/o i/o gnd tdi i/o tms nc tck i/o i/o i/o i/o gnd 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 gnd nc nc i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o v ccio1 i/o i/o gnd gnd i/o i/o i/o i/o v cc i/o i/o i/o i/o i/o i/o i/o i/o nc i/o v ccio1 gnd i/o (3) nc v ccio2 i/o nc i/o nc i/o nc i/o i/o i/o i/o i/o i/o i/o v ccio2 i/o i/o i/o gnd tdo i/o i/o i/o i/o i/o i/o i/o nc i/o i/o i/o i/o v ccio2 (1) - global output enable (2) - global clock (3) - global set/reset (4) - clock divide reset (5) - datagate enable
xc2c128 coolrunner-ii cpld 18 www.xilinx.com ds093 (v3.2) march 8, 2007 product specification r additional information additional information is available for the following coolrunner-ii topics: ? xapp784: bulletproof cpld design practices ? xapp375: timing model ? xapp376: logic engine ? xapp378: advanced features ? xapp382: i/o characteristics ? xapp389: powering coolrunner-ii ? xapp399: assigning vref pins to access these and all application notes with their associ- ated reference designs, click the following link and scroll down the page until you find the document you want: coolrunner-ii data sheets and application notes device packages revision history the following table shows the revision history for this document. date version revision 10/01/02 1.0 initial xilinx release. 5/19/03 2.0 added bin 6, 7 characterization data. 8/25/03 2.1 edit package diagram, other minor formatting edits. 01/26/04 2.2 update links. 03/01/04 2.3 fixed cropping on figure 6. 7/30/04 2.4 added pb-free documentation. 10/01/04 2.5 add asynchronous preset/reset pulse width specification to ac electrical characteristics. 01/30/05 2.6 change to i ccsb max for commercial and industrial. 03/07/05 2.7 delete -4 speed grade. modifications to table 1, iostandards. 04/21/05 2.8 recharacterization of ac specifications 06/28/05 2.9 move to product specification. 03/20/06 3.0 add warranty disclaimer. add note to pin descriptions that gck, gsr, and gts pins can also be used for general purpose i/o. replaced figure 3 with a higher resolution graphic. 02/15/07 3.1 corrections to timing parameters t f , t ct , t din , t gts , t oem and f toggle for -6 speed grade. corrections to t din , t gck , t en , t sui , t ecsu , t f , t oem , f ext1 , and f ext2 for the -7 speed grade. values now match the software. there were no changes to silicon or characterization. change to v ih specification for 2.5v and 1.8v lvcmos. 03/08/07 3.2 fixed typo in note for v il for lvcmos18; removed note for v il for lvcmos33.

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